1. Field of the Invention
The present invention pertains to a method of etching silicon nitride with high selectivity relative to various oxides in a high density plasma chamber. In addition, the present invention relates to etching of silicon nitride spacers having rounded top corners and an extended exterior tail at the spacer base.
2. Brief Description of the Background Art
There are numerous applications in semiconductor processing where it is desirable to etch silicon nitride with high selectivity relative to silicon oxide. For example, such selectivity is particularly important during the formation of capacitive structures used in DRAMS and SRAMS, and in various logic devices where there is a gate present. Frequently there is a need to etch a silicon nitride spacer which is adjacent to an exposed oxide layer, or where etching of the nitride spacer itself exposes an oxide layer to the etchant plasma. In these instances, it is desirable to be able to etch the silicon nitride spacer at an etch rate which is at least 10 times or more rapid than the etch rate of the exposed oxide, i.e. the selectivity for nitride relative to oxide is at least 10:1.
Etching of a nitride spacer adjacent to an oxide gate is one of the critical challenges in a high density plasma processing chamber of the kind used to etch semiconductor features having a critical dimension in the range of about 0.1 xcexcm. The high density plasma necessary for other etch processing, to produce features of this size, typically exhibits a density of about 1011 exe2x88x92/cm3. This plasma density tends to produce a significant ion bombardment of the substrate being etched, which reduces the selectivity of silicon nitride etch relative to silicon oxide etch. To avoid the ion bombardment of the substrate, the plasma density can be lowered; however, there are limitations on the minimum plasma density which can be achieved in a high density plasma chamber. Further, a lower density plasma affects the amount of energy available to generate the chemical etchant species used for etching of the nitride. This slows down the etch rate in general. It would be possible to etch a device structure such as silicon nitride spacers in a different, lower plasma density etch chamber than other device features, but this complicates the overall device fabrication process. It might be possible to lower the plasma density by increasing the range of operating pressures within the high density plasma process chamber, but this requires substantial equipment modification. Further, in view of such equipment modification, general process parameters for various known processes would have to be reevaluated, also an expensive proposition.
An example of a structure which requires selective etching of a nitride relative to an oxide is the etching of silicon nitride spacers in a capacitive structure, where it is desired to produce a rounded corner shape at the top of the silicon nitride spacer, without affecting an adjacent oxide structure. U.S. application Ser. No. 09/797,355, of Tuman Earl Allen III, filed Feb. 28, 2001 and published Jul. 26, 2001, describes a method of etching such a structure. The structure is shown in the Allen reference in FIGS. 4 and 5, which are generally illustrated in FIGS. 1A and 1B of the present application. With respect to applicants"" FIG. 1a, a wafer fragment 100 comprises a substrate 102 having a transistor gate construction 105 formed over substrate 102. Substrate 102 may comprise, for example, monocrystalline silicon lightly doped with a P-type dopant. Transistor gate structure 105 comprises a thin silicon dioxide layer 104, a polycrystalline silicon layer 108, a metal-silicide layer 110, and an insulative cap 112. Metal silicide layer 110 may comprise, for example, titanium-silicide or tungsten-silicide, and insulative cap 112 may comprise, for example, a second silicon dioxide layer. In the structure shown, silicon dioxide layer 104 extends beyond lateral peripheries of gate construction 105. A silicon nitride layer 106 is formed over the entire surface of wafer fragment 100, so that it covers both silicon dioxide layer 104 and transistor gate structure 105. FIG. 1B shows the FIG. 1A wafer fragment 100, after etching of silicon nitride layer 106 to produce sidewall spacers 107 on the sidewalls 114 of gate construction 105.
In one example of the prior art, etching of the silicon nitride layer 106 is carried out using a complicated combination of etch steps, including a process chamber cleaning step between a first etch step and a second etch step. The process chamber cleaning step is designed to remove etch byproducts which build up on process chamber walls between the first (physical-type) etch step and the second (chemical-type) etch step. The first etch step is highly physical (non-selective), and is used to etch through the majority of a material, and the second, a chemical-type etch (highly selective) is used to etch through a remainder of the material. Both the physical-type etching and the chemical-type etching use a plasma source gas comprising CF4/HBr. However, the physical-type etching is carried out with the application of less power to the plasma source, a significantly higher application of bias power to the substrate, and at a significantly lower process chamber pressure than the chemical-type etching.
One skilled in the art will recognize that the cleaning step between the first and second etch steps is likely due to polymer build up which is produced due to the presence of carbon and HBr in the source gas for etchant plasma production. The presence of the carbon and HBr enables the production of passivating polymers which protect both exposed oxide surfaces and etched silicon nitride surfaces. This enables the production of rounded corners on the upper edges of the silicon nitride spacers, while protecting adjacent oxide layers during etching of the silicon nitride spacers. However, the use of a fluorocarbon as a plasma source gas is unacceptable for etching silicon nitride features in the presence of an oxide layer of less than about 100 xc3x85, the thickness of a typical silicon oxide gate layer.
A cleaner process for etching silicon nitride in the presence of silicon oxide is also known in the art. Such a process provides the selective plasma etching of silicon nitride in the presence of silicon or silicon oxides using mixtures of NF3 or SF6 and HBr and N2. In particular, a plasma-maintaining gas that includes N2 having an inflow rate of at least 10 sccm is used to provide etch-depth uniformity across the workpiece. The plasma-maintaining gas further includes HBr and one or both of NF3 and SF6. The process chamber used during etching utilizes a single electromagnetic energy source operatively coupled to a cathode and anode for producing an electromagnetic field between the opposed faces of the cathode and anode. This process chamber is considerably different from the DPS plasma processing chamber described in the Allen reference. For further information about this cleaner process, the reader is directed to U.S. Pat. No. 5,877,090 to Padmapani Nallan et al., issued Mar. 2, 1999.
Applicants developed a process for selectively etching silicon nitride relative to oxides which could be carried out in a high density plasma process chamber, is capable of producing plasma densities of at least 1011 exe2x88x92/cm3. This would permit fabrication of silicon nitride spacers in the same process chamber as that used to fabricate 0.1xcexc critical dimension semiconductor features. The general problem to be solved was that a high density plasma tends to provide more ion bombardment of the substrate surface, making it more difficult to employ an etch mechanism which permits highly selective etching of silicon nitride relative to an oxide. Although plasma density could be reduced by expanding the operational capabilities of a single plasma processing chamber, this would be a particularly expensive proposition. In the alternative, use of a plasma which provides particularly large quantities of passivation materials may be used; but, this is a xe2x80x9cdirtyxe2x80x9d process which coats the surfaces of the process chamber, requiring cleaning steps which may cause downtime or which may affect the device when substrate cleaning is conducted insitu.
It is clear that it would be highly desirable to have a process which can be carried out in a high density plasma processing chamber, which provides high selectivity for etching silicon nitride relative to an adjacent oxide, at an etch rate which is commercially viable. In addition, it would be particularly valuable if such a process were capable of producing a silicon nitride spacer with rounded top edge corners and a long extended xe2x80x9ctailxe2x80x9d toward the bottom outer edge of the nitride spacer.
We have developed a method of selectively etching silicon nitride relative to oxides in a high density plasma chamber of the kind presently known in the art. We have obtained selectivities for silicon nitride:silicon oxide in the range of about 15:1 to about 26:1, where the silicon nitride etch rate varied, depending on overall etch conditions, from about 456 xc3x85 per minute to about 200 xc3x85 minute. In some instances no etching of the silicon oxide was observed, so that the selectivity is infinity. However, in such instances, the silicon nitride etch rate was typically below about 200 xc3x85 per minute. We have employed the method in the etching of silicon nitride spacers for sub 0.25 xcexcm devices, where the spacers are adjacent to exposed oxides during the etch process. We have obtained silicon nitride spacers having rounded top corners and an extended xe2x80x9ctailxe2x80x9d toward the bottom outer edge of the nitride spacer.
The method employs a plasma source gas which typically includes SF6, HBr, N2, and optionally, O2.
Typically, the volumetric flow rate ratio of HBr:SF6 ranges from about 1.8:1 to about 4:1. More typically, this volumetric flow rate ratio ranges from about 1.8 to about 2.0. The etch selectivity of silicon nitride to oxide increases and the etch rate of silicon nitride increases as the N2 flow rate is increased at a given flow rate ratio of HBr:SF6, up to an N2 flow rate which is about 0.5 times to about 0.6 times the SF6 flow rate. The etch rate of silicon nitride increases slightly, while the selectivity of silicon nitride to oxide increases up to about 15% when O2 is added to the plasma source gas, up to an O2 flow rate which is about 0.5 times to about 0.6 times the SF6 flow rate.